Timing requirements to a part of a circuit

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kaz, I'm using old version of cookbook (https://vk.com/doc-93602802_401608943?hash=1d128a921cdd322f95&dl=bd60b7ecbf49a6ca84), so there is some difference in projects, in old version they use pipelined multiplier, clocked by fast_clk. So when I click summary setup I can get some information about multiplier's set of registers. Of course if we use mult without pipelining we won't get any setup information. Which command is intended for enable only? OK, I'll look for it in Altera's documents...

What I expect is to get some information about enabled registers: are requirements met or not, slacks, etc... If it's possible, of course.

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The two documents of cookbook have identical diagrams for enable multicycle example. The only difference is the figure number 1-16 & 1-18

sdc command for enable multicycle is given directly at bottom of page and has two parts multicycle and fanout.

If project timing passes then it means all paths are ok including those on enable. To specifically find out about any given path then just follow the usual approach either in TQ GUI or by direct commands.

I am not clear what do you mean by "without pipeline". There are registers on either side of mults, so these are valid timing paths.