Timing requirements to a part of a circuit

You can define multi cycle paths to allow the fitter more flexibility if such things exists. You can also place logic lock regions to restrict specific parts of the design to specific regions of the chip. This often has the effect of prioritising these parts within the area, and any other non-logic-locked logic will fit in around the locked areas. This will help your timing by keeping an entity close together rather than spreading it apart.

I think it's not a good strategy to optimize whole design in each case. For example, let it consists of several clock domains. One of these domains contains a part which must be optimized (a lot of logic between FFs). Of course we can set a constraint to a whole domain, but from my point of view this approach could lead to a non-optimal routing of other parts of the design. I mean that one part of the domain might operate exactly with clock frequency, while others might use enables and their actual operating frequencies could be much lower then clock frequency, that's why those parts don't need optimization.

Please could you clairfy? if your whole design is synchronous then you should just be able to set timing constraints to the clocks and it will do the work for you. Clock domain crossings need some consideration, but sometimes false paths are sufficient.