Timing problems?? help

Hi, I have a problem, I created a system in SOPC with Nios II, Sram, Switch, LEDs and a custom interface to an external component.

The custom component implemented in VHDL is linked to the system with NIOS in Quartus,

The clock is connected to the system is 50 MHz (DE1 board), the external component has a 2.5-MHz clock through a divider.

Timing problems that I see in the report, there are many paths not correct.

Timing analyzer -> Fast Model-> Clock Hold -> Not operational: Clock Skew> Data Delay -> From ... To .. Actual and Shorte P2P TIME

Timing analyzer -> Slowt Model-> Clock Hold -> Not operational: Clock Skew> Data Delay -> From ... To .. Actual and Shorte P2P TIME ecc...

How can I solve this problem?

Thanx.

p4ride