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NShan12's avatar
NShan12
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Timing issues on DFF feedback loop.

Hello, I wanted to know if the output of DFF in the attached design leads to any timing problems. What happens to DFF output if both Preset and Clear are active at the same time? CLK is 32 MHz....
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


You may check the Compilation report > Timing Analyzer to see if there is any timing violation or timing related problem in the design. Besides this, do not simultaneously activate the CLEAR and PRESET inputs. You may simulate the design to verify the output of the DFF.


Thanks

Best regards,

KhaiY


  • NShan12's avatar
    NShan12
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Thank you for your reply.

    In the larger design which I am trying to simulate, I see that the output of DFF with "Q" output connected directly to "D" input results in Unknown value (X) on Q output.

    So, I want to know how to analyse the timing for a DFF where Q is directly connected back to D. Since I see that the output is X, I would like to know how this could be solved.

    Hope my explanation is clear.