Timing for MAX 10 ADC Control Core Only interace logic

Hi, (note following update post about clocks) Attached is a vhdl file that I got working. I cut it down a bit, so can't guarentee it'll compile first time, but the gist is there. Is reads 2 channels periodically, using the raw version of the ADC. ADC and PLL generated using Quartus 16/17 Tools->IP Catalog. PLL converts 8MHz to 2MHz, and is there only because the ADC won't work without the PLL. The BIG problem I had was what an Altera FAE has confirmed to me is a bug in Quartus: the IP core Wizard for the ADC generates 2 sets of files: a simulation folder and a synthesis folder. Only the SYNTHESIS ADC folder contains the IP Core customisations you specified - the simulation folder just contains a blank ADC template, which naturally does not simulate. Currently I'm compiling the synthesis files manually in ModelSim, but a simpler way would likely be to just copy the synthesis files into the simulation folder. Hope this helps, Rob