Timing for MAX 10 ADC Control Core Only interace logic

I'm running into the same problem and I would love to find someone who has a VHDL file that correctly instantiates the Max 10 ADC. I would also like to have some sharp words with whoever thought it was a good idea to make it a Qsys only component.

I have a Max 10 ADC watching 9 analog signals - 4 power supplies and 5 actuator FET monitors. The logic is dead simple - really just a set of digital comparators with hysteresis. What I want from the ADC is set of 9 12-bit values and an update signal to tell the downstream logic a new sample set is ready.

Even a simple example of how to instantiate and drive this thing in VHDL would be great, as I have tried everything I can think of. Quartus knows it is supposed to be there too, as it shows up in the hierarchy.