Timing contraint on top module and sub-module design.

In a classic integration all submodules lose boundaries and the compiler views all the units as one single program. io then is known as those top level ports that connect to fpga pins.

When designing submodules there is really no need for io timing because the pins are decided only at top level. However for very serious work(and most designers don't do this) you need to add temporary registers to inputs so that you model the connecting input module at integration. Remember timing tools only check paths between registers plus io (pins) if you tell it the data/clk relation.

For submodule level io is never needed and I usually cut these paths but may add temporary registers to inputs.

If your submodule passes timing then it will be refitted at top level and may or may not behave in similar way when standalone. But it must at least pass timing well when standalone.

How about my design in my submodule and sub-sub module? you mean i don't need time constraint for my submodule and sub-sequence submodule?

I am confussed, could you elaborate?

io means pins and not ports of submodules.

Timing at submodule level for ports is irrelevant and a burden that should not be allowed.