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Altera_Forum's avatar
Altera_Forum
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14 years ago

Timing contraint on top module and sub-module design.

Hi, I've just started learning to time constraint my design, so i have a few questions i would like to clarify. 1) Do i need to redo the time constraint on the I/O port of my sub-module if...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How about my design in my submodule and sub-sub module? you mean i don't need time constraint for my submodule and sub-sequence submodule?

I am confussed, could you elaborate?