timing constraints for SPI (or UART)

kaz,

thank you for your help.

the SPI clock (50 M) is also an input to my FPGA, not its output. Also, since it is very slow compared to my system clock of 333.33 M, I just treat as a regular signal in my design and sample it with my system clock. So I did not declare it as a clock in .sdc file. Should I?

I detect falling edges on the spi clock and have to prepare data such that it is ready to be sampled by the host on the positive edges of spi clock.

Assuming tsu and th as target dff parameters, how and what constraints do I need to add?

Regards,