Timing Behavior of Remote Update IP After Reset on Cyclone 10 GX (10CX150YF672E5G)

As per the suggestion, I installed Quartus Prime Pro 25.1-129 and created a simple project to verify the behavior. The design includes the Remote Update IP and Clock PLL IP, as described earlier in this thread. The issue persists: the Remote Update IP returns all ones for all read data immediately after the busy signal deasserts.

Specifically, after configuration completes, I wait for the busy signal to deassert, then read the current configuration boot address and reconfiguration trigger conditions. All read data returns 0xFFFFFFFF. However, if I wait approximately 300 µs after busy deassertion, reads and writes work correctly.

The latest SignalTap capture is attached.

 

The latest SignalTap capture is attached. I am also attaching my sample project for your reference, so you can reproduce the issue directly. It is a minimal, working design that uses an external clock and reset with three LED outputs, Clock PLL IP, and Remote Update IP. The PLL locked signal is used as reset with proper clock domain synchronization.

If possible, could you share your project that worked as expected?

I am using a Cyclone 10 GX FPGA with part number 10CX150YF672E5G.


Regards,
Sumanth S