timing analyzer relationship

Just set_input_delay and set_output_delay? You have clock constraints as well, I presume. Are you using virtual clocks correctly for your I/O? Are these I/O paths or internal paths?

It would help to just see the .sdc file and details on the failing path(s).

EDIT: just noticed there's very large skew on the paths with the halved clock relationship, which could indicate a gated clock and an incorrect use of device clock resources. Definitely need more detail and info.