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NShan12's avatar
NShan12
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4 years ago

Timing analysis error on Asynchronous control signals

Hello, In my design, there is an asynchronous bus between FPGA and Microcontroller (Master). FPGA uses the edges on the signals WRN (Write active) and ALE (Address Enable) to classify if the signa...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi Naveen,


"In any case, how can I solve the unconstrained clock warning by the timing analyzer"

- Assuming I understand your question, have you able to constrain all the clocks in sdc? This should reflect in Timing Analyzer


  • NShan12's avatar
    NShan12
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    Hi,

    Yes, all the clocks (on IO ports, generated clocks, virtual clocks etc.) are constrained in the SDC file. Since WRN and ALE are not clocks only false path constraints exist on them.