Timing analysis error on Asynchronous control signals

Yes, I had set false paths on them. But Timing analyzer report still shows these two signals as unconstrained clocks in the clock status summary.

My Code:

--somewhere in the architecture

PROCESS ( ale, adbus )
BEGIN
IF ( ale'event AND ale = '0' ) THEN
address <= adbus;
END IF ;
END PROCESS;

PROCESS ( wrn, clearn, adbus )
BEGIN
IF clearn = '0' THEN
data<= "0000000000000000" ;
ELSIF ( wrn'event AND wrn = '1' ) THEN
data <= adbus( 15 DOWNTO 0 );
END IF ;

END PROCESS

I am using the edges of ALE and WRN to identify if it is address or data on the adbus, and the tool thinks these are clocks.

There are also warnings:

Warning (332060): Node: wrn was determined to be a clock but was found without an associated clock assignment.

Warning (332060): Node: ale was determined to be a clock but was found without an associated clock assignment.