Timer Period not correctly

Question

Hi all, my goal is to set a timer with a period time of 1ms and start it. After the time is elapsed it should rise an IRQ (once). The timer itself with interrupt works, but the time is always about 6 to 8us. regardless what i write into the timer period registers? I also tried to set 80'000 (80MHz clock) but nothing changed on the 6 to 8 us.  qsys settings:  Period: 1us size: 32bit Hardware Options: Full featured  Here the code for the timer:  init:    
alt_ic_isr_register(HIRES_TIMER_IRQ_INTERRUPT_CONTROLLER_ID, HIRES_TIMER_IRQ, hires_timer_ISR, NULL, NULL);
  note: i made this according to the BSP generator for my niosII / uC-OSII project  irq:  
void hires_timer_ISR() {
  IOWR_ALTERA_AVALON_PIO_DATA(DEBUG_BASE, 0);
  IOWR_ALTERA_AVALON_TIMER_CONTROL(HIRES_TIMER_BASE, 0x0000); // disable IRQ
}
  start the timer: 
// set debug io
        IOWR_ALTERA_AVALON_PIO_DATA(DEBUG_BASE, 1);
        // set period
        IOWR_ALTERA_AVALON_TIMER_PERIODL(HIRES_TIMER_BASE, 0x03E8);
        IOWR_ALTERA_AVALON_TIMER_PERIODH(HIRES_TIMER_BASE, 0x0000);
        // Start timer, single, with IRQ
        IOWR_ALTERA_AVALON_TIMER_CONTROL(HIRES_TIMER_BASE, 0x0005);
  Thanks in advice, Thomas

altera_forum · Answer

When using a timer as a one shot, you need to write the wanted delay in the snapshot counter registers, not the period registers.

When you send the "start" command, the timer counts down from the value currently stored in the snapshot counter. The period value is only copied in the counter once the counter reaches 0.

altera_forum · Answer

Hi Daixiwen,

although for me a "snapshot" is like a snapshot (like photography) of the timer count, now i know why there is also a write to those registers. Maybe my englisch isn't good enough.

I will try that as soon as possible.

Thanks you for your reply

altera_forum · Answer

English isn't my mother tongue either but I agree that "snapshot" is a poor choice of words in that case. If you check the timer's datasheet you will see that they are read/write registers.

altera_forum · Answer

Ok, I tried to do it like this:          // set on shot time
        IOWR_ALTERA_AVALON_TIMER_SNAPL(HIRES_TIMER_BASE, 0x03E8);
        IOWR_ALTERA_AVALON_TIMER_SNAPH(HIRES_TIMER_BASE, 0x0000);
        // Start timer, single, with IRQ
        IOWR_ALTERA_AVALON_TIMER_CONTROL(HIRES_TIMER_BASE, 0x0005);
  and then also like this:         // set on shot time
        IOWR_ALTERA_AVALON_TIMER_SNAPL(HIRES_TIMER_BASE, 0x03E8);
        IOWR_ALTERA_AVALON_TIMER_SNAPH(HIRES_TIMER_BASE, 0x0000);
        IOWR_ALTERA_AVALON_TIMER_PERIODL(HIRES_TIMER_BASE, 0x03E8);
        IOWR_ALTERA_AVALON_TIMER_PERIODH(HIRES_TIMER_BASE, 0x0000);
        // Start timer, single, with IRQ
        IOWR_ALTERA_AVALON_TIMER_CONTROL(HIRES_TIMER_BASE, 0x0005);
  always with the same behavour, about 6 to 8us until the IRQ is served....  In the data sheet it is written on the control register bit CONT:  "When the counter reaches zero, it reloads with the value stored in the period registers, regardless of the  CONT  bit" Thus I would assume that with the second shot the time should be right?  Also a test with writing a 7 to the Control register witch also enables the CONT bit (continuous) just "activates" the IRQ just once and not every 1000ms???  Is there maybe a problem with the period setting in QSYS? =&gt; Set to 1us assuming the timer decrements every 1us meaning with 1000 set to period/snapshot register counter reaches 0 at 1ms.

altera_forum · Answer

Yes I think it's a problem with the QSys settings. The value you put in the period and snapshot registers are always expressed in clock cycles. This means that if you have a 80MHz clock, you need to write 80000 to get a 1ms timer. The value you write now is too small for a 1ms delay. The period setting that you set in QSys only sets the initial value of the period register. Remember also to enable the "writeable period" option on so that you have the possibility to modify the period register.

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Timer Period not correctly

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