Forum Discussion
Sameer-sahu
Occasional Contributor
1 year agoTimeQuest Ignoring create_generated_clock for SPI Clock Derived from Gated Divide-by-4 Signal (sck_r
Hi all, I'm encountering a persistent issue with Quartus Prime and TimeQuest Timing Analyzer where my create_generated_clock constraint is being ignored, even though I'm defining it on a clean, regi...
RichardT_altera
Super Contributor
1 year agoThank you sstrell for answering.
Hi OP,
Does sstrell's suggestion helps?
Do you have further inquiry?
Regards,
Richard Tan