Timequest constraints for a dynamically phase-shifted PLL

So are you saying you have created extra logic or only applied timing constraints to achieve 2)? I am assuming the latter in which case the following comments apply otherwise I have got hold of the wrong end of the stick.

Applying your constraints doesn't stop launch register to latch register transfers happening at every clock edge including those which may not meet setup and hold times of the latch register. Your constraints may satisfy TimeQuest but they do not alter the physical reality.

e.g. If you use the typically advised 2 stage register chain to re-sample a signal from one clock domain to another asynchronous domain, it is usual to cut the timing to prevent TimeQuest from analyzing the transfers (since they would fail). However, this does not actually in any way stop metastability from occuring on the first register in the chain. It's a physical reality which cannot be somehow "fixed" by TimeQuest.