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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Do you mean changing: 

always_ff @(posedge dynshift_clk)
begin
    d <= c;
end

...to: 

always_ff @(posedge dynshift_clk)
begin
    if (clock_enable == 1'b1)
        begin
            d <= c;
        end
    else
        begin
            d <= 1'b0;
        end
end

???