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Honored Contributor
Honored ContributorTimequest constraints for a dynamically phase-shifted PLL
I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_ForumHonored Contributor
Honored ContributorI read your "generating appropriate clock enables to sample the signal with enough setup and hold time for each clock transfer at each phase setting" to mean do I have the timing constraints properly in place for all phases by having only two ‘set_multicycle_paths’ in my Timequest constraints file (because it seems unlikely at first glance that those two would cover all eight phases, but they appear to me to do).
So, do you mean am I using clock enables AKA gated clocks? I.e. such as those described in the “Clock Enable Multicycle” section of ‘mnl_timequest_cookbook.pdf’, page 25 {document revision 2017.11.21}]? If that’s what you meant, I am not using any gated clocks. Thanks for your continued interest.
