Timequest constraints for a dynamically phase-shifted PLL

Timing errors can sometimes occur when paths are inappropriately or mistakenly cut either through setting an exclusive clock group or by explicitly cutting a path (I know, I have done this myself). If there are or should be valid clock transfers which should be analyzed between each of the phases and some other reference clock, then that clock presumably could be included in each of the exclusive groups.

Maybe something like (though I haven't tried this):

set_clock_groups -logically_exclusive -group {apg_phase00_045 clock_x} -group {apg_phase00_090 clock_x} -group {apg_phase00_135 clock_x} -group {apg_phase00_180 clock_x} -group {apg_phase00_225 clock_x} -group {apg_phase00_270 clock_x} -group {apg_phase00_315 clock_x} -group {drv1|mypll_apg_ph0|*|altera_pll_i|cyclonev_pll|co unter[0].output_counter|divclk clock_x}