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Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi de-em,

Once the PLL is locked on a new phase, it will output correctly on most of the eight phases, but on some of the phases (varies by build which ones they are) the output randomly comes in one latching-clock early or late. This suggests to me that it is a metastability issue - as if my logically-exclusive timing constraints were NOT being analyzed correctly by Timequest and/or the fitter.