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Altera_Forum
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7 years ago

Timequest constraints for a dynamically phase-shifted PLL

I've been trying to properly constrain a design that uses dynamic phase shifting of an instance of an altera_pll core that I created. I.e. to enable phase-shifting I checked the "enable access to dy...
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Altera_Forum
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7 years ago

Hi vlrean,

The repro is purely in the domain of my synchronous logic driven by the dynamically phase-shifted PLL before our device is even hooked up. Not that it would matter anyway - our industrial device has no clock, so no source-synchronous constraints such as set_output_delay are needed. :)

I should add that since I was concerned that the phase shifts weren't exactly every 45 degrees, I was able to derive what Quartus thinks they are via the technique discussed here (thanks, Brad!): https://www.alteraforum.com/forum/showthread.php?t=4567 (https://www.alteraforum.com/forum/showthread.php?t=4567)

...and that didn't help when I specified them as such, unfortunately. FYI, what I did was instantiate a special just-for-investigation PLL that was statically phase-shifted so I could see what values Quartus created for passing to the '-phase' parameter, then I used those values for the non-investigation dynamically phase-shifted PLL instantiation.

What I really need is a timing guru to tell me whether my constraints look okay and if the '-logically_exclusive' does actually work for dynamically phase-shifted PLLs. Anyone?

-Eric