TimeQuest Constraint on PLL

I have a fairly trivial .sdc file which works with the following code:

# Constrain the external FPGA clock from oscillator

create_clock -period 20 -name clk [get_ports CLK]# Derive pll clocks & clock uncertainty

derive_pll_clocks

derive_clock_uncertainty

Now, I tried the following code and simply will not work. # -------------------------------------------------------# Constrain the Phase Locked Loop Master Clock = 50 MHz# -------------------------------------------------------

create_generated_clock -add

-source Upll|altpll:altpll_component|PLL50_LOCK_altpll:auto_generated|pll1|inclk[0]

-name Upll|altpll:altpll_component|PLL50_LOCK_altpll:auto_generated|pll1|clk[1]

-master_clock clk

[get_pins Upll|altpll:altpll_component|PLL50_LOCK_altpll:auto_generated|pll1|clk[1]]

Now, in the above code (which is downsized font to make it fit on screen), I am referencing a PLL which I am instantiating with VHDL that was generated from the Mega Wizard.

Upll: entity work.pll50_lock(syn)

port map (

inclk0 => inclk0,

c0 => clk1MHz,

c1 => c1,

locked => locked

);

I have read Altera's documentation carefully . . . . and find the TimeQuest documentation to be vague on the naming conventions. The example given with a symbol rather than verilog or VHDL example is quite trying.

I am wondering if anyone can see the problem with my code above to manually constrain the PLL clock.

Thank you. James