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Altera_Forum
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14 years ago

TimeQuest Constraint on PLL

I have a fairly trivial .sdc file which works with the following code: # Constrain the external FPGA clock from oscillator create_clock -period 20 -name clk [get_ports CLK]# Derive pll clocks ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

If they're independent files, then you're missing the create_clock. The generate clock has to be based off another clock.

Assuming it's some of both, copy out of the TimeQuest messages from your derive_pll_clocks that worked. Derive_pll_clocks is not a real .sdc constraint, but a script that runs other .sdc commands. It tells you exactly what it ran, so if it worked, copy and paste from that.

Besides the space in auto(which I assume is a cut and paste issue, as I've seen that here), you seem to be matching name conventions. You can either do entity:instance or just instance, i.e.:

Upll:pll50_lock|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|inclk[0]

or

pll50_lock|altpll_component|au o_generated|pll1|inclk[0]

But in yours, it's using only entity on the top-instance and the PLL1 instance. Again, start with what derive_pll_clocks does.