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Honored Contributor
Honored ContributorTimeQuest Constraint on PLL
I have a fairly trivial .sdc file which works with the following code: # Constrain the external FPGA clock from oscillator create_clock -period 20 -name clk [get_ports CLK]# Derive pll clocks ...
Altera_ForumHonored Contributor
Honored ContributorWhat do you mean it doesn't work?
Doesn't derive_pll_clocks already constrain this PLL output? Why are you adding another one? If it's a syntax issue, then in TimeQuest messages, go to the derive_pll_clocks and just copy from there, as it gives the exact syntax for constraining the PLL. Right now your assignment is after derive_pll_clocks, so you're constraining something that already has a generated clock on it. Either put the "-add" option on your generated clock, although it will need a different name, or put it before derive_pll_clocks, which won't constrain a PLL output if it already exists. The hierarchy names are annoyingly long, but you shouldn't ever have to enter them manually.
