TimeQuest Constraint on PLL

As I mentioned & declared previously, the code below DID WORK:

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# Constrain the external FPGA clock from oscillator

create_clock -period 20 -name clk [get_ports CLK]# Derive pll clocks & clock uncertainty

derive_pll_clocks

derive_clock_uncertainty

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The code below (separate from the code above, in its own SDC file) did NOT WORK:

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#-------------------------------------------------------# Constrain the Phase Locked Loop Master Clock = 50 MHz# -------------------------------------------------------

create_generated_clock -add

-source Upll|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|inclk[0]

-name Upll|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|clk[1]

-master_clock clk

[get_pins Upll|altpll:altpll_component|PLL50_LOCK_altpll:aut o_generated|pll1|clk[1]]

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What I am really after is this: is the whole instantiation path necessary? It appears that it is, but even with that, I still would not work.

James