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Honored ContributorTimeQuest – Problem with Crossing Clock Domains
Hi everyone!
I use Cyclone III (speed grade C8). There are two clock domains in my project. The first one is clocked by output frequency rx_outclock = 40 MHz of ALTLVDS_Rx module. Option “Use External PLL” of ALTLVDS_Rx is disabled. The second domain is clocked by 50 MHz which is formed by main PLL of project. Here is the report of clocks in my project: https://www.alteraforum.com/forum/attachment.php?attachmentid=5352 Here is the contents of .sdc file: https://www.alteraforum.com/forum/attachment.php?attachmentid=5353 The project was compiled. Many negative slacks of Setup appeared on the boundary between clock domains (launch and latch clocks belong to different clock domains). Here is an example of worst-case timing paths: https://www.alteraforum.com/forum/attachment.php?attachmentid=5354 The worst-case setup slack is -2,247 ns. You can see from the report that the relationship of launch and latch clocks is only 1.562 ns. This is because of Quartus automatically assigned phase shift = -22,5 deg for launch clock (see the report of clocks above). I decided to increase the relationship between launch and latch clocks (i.e. “shifting the window”) by command (added in .sdc file): set_multicycle_path -setup -from [get_clocks inst4|altlvds_rx_component|auto_generated|lvds_rx_pll|clk[1]] -to [get_clocks inst2|altpll_component|auto_generated|pll1|clk[0]] 2 After recompilation all negative slacks of Setup was eliminated and relationship between launch and latch clock became 16,652 ns. But many negative slacks of Hold appeared. Here is an example of worst-case timing paths after recompilation: https://www.alteraforum.com/forum/attachment.php?attachmentid=5355 How can I fix timing problems described above ? Or may it be impossible to eliminate them ? Thank you.5 Replies
Altera_ForumImplementing DCFIFO resolved all timing problems in project.
Many thanks to kaz and rysc.- Altera_Forum--- Quote Start --- Are both PLLs driven by the same source clock? (Otherwise it won't work at all) --- Quote End --- I don't know exactly. In fact, 50 MHz is formed by ALTPLL megafunction and this PLL is fed by external onboard oscillator. ALTLVDS_Rx module was created with disabled option "Use external PLL". Therefore one more PLL is incorporated in ALTLVDS_Rx and this hidden PLL may be fed by the same external onboard oscillator indirectly. But PLL inside ALTLVDS_Rx may be fed by RX_INCLOCK input (i.e. from lvds clock input). Therefore I can't answer your question unambiguously. I think rx_outclock of ALTLVDS_Rx and 50 MHz of ALTPLL must be treated as related. Now I'm introducing DCFIFO in my project. I'll post result as soon as possible. Many thanks for your advices.
- Altera_Forum
If they're related, and you have logic to handle the case when you clock in the same data(one out every 5 latch clock cycles will be a repeat) it can be done, but I agree, an asynchronous FIFO makes it significantly easier. Just adds a little latency and logic.
- Altera_Forum
You need to use dc fifo to cross clock domains. As simple as that.
- Altera_Forum
How do you go from a 40MHz clock to a 50MHz clock? Do you have logic that determines which latch clock is a repeat and ignores it?
Are both PLLs driven by the same source clock? (Otherwise it won't work at all) Go to Assignments -> Settings -> Fitter Settings and turn on Optimize hold Timing and check multicorner analysis. That being said, you're asking it to add 15ns of delay. If the router adds 15ns of delay at the slow corner, assume that's at least 30ns of delay at the fast corner, and it will fail setup. Because of the relationships, what you're asking is impossible. I would just phase-shift your 50MHz clock forward a bit, say 3ns or something like that(it gets confusing due to the different clock periods, so you may need to draw it out and find the best one.)
