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Altera_Forum
Honored Contributor
Honored ContributorTimeQuest – Problem with Crossing Clock Domains
Hi everyone! I use Cyclone III (speed grade C8). There are two clock domains in my project. The first one is clocked by output frequency rx_outclock = 40 MHz of ALTLVDS_Rx module. Option “...
Altera_ForumHonored Contributor
Honored ContributorImplementing DCFIFO resolved all timing problems in project.
Many thanks to kaz and rysc.
