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Honored Contributor
Honored ContributorTimeQuest – Problem with Crossing Clock Domains
Hi everyone! I use Cyclone III (speed grade C8). There are two clock domains in my project. The first one is clocked by output frequency rx_outclock = 40 MHz of ALTLVDS_Rx module. Option “...
Altera_ForumHonored Contributor
Honored ContributorIf they're related, and you have logic to handle the case when you clock in the same data(one out every 5 latch clock cycles will be a repeat) it can be done, but I agree, an asynchronous FIFO makes it significantly easier. Just adds a little latency and logic.
