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Are both PLLs driven by the same source clock? (Otherwise it won't work at all)
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I don't know exactly.
In fact, 50 MHz is formed by ALTPLL megafunction and this PLL is fed by external onboard oscillator.
ALTLVDS_Rx module was created with disabled option "Use external PLL". Therefore one more PLL is incorporated in ALTLVDS_Rx and this hidden PLL may be fed by the same external onboard oscillator indirectly. But PLL inside ALTLVDS_Rx may be fed by RX_INCLOCK input (i.e. from lvds clock input). Therefore I can't answer your question unambiguously.
I think rx_outclock of ALTLVDS_Rx and 50 MHz of ALTPLL must be treated as related.
Now I'm introducing DCFIFO in my project.
I'll post result as soon as possible.
Many thanks for your advices.
Honored Contributor
