the signaltab problems

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And i want to know if the SignalTab will affect the original logic in the fpga

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Necessarily.

You can't tap the high speed LVDS input signals. Recording the deserialized data should be possible, and sufficient to debug LVDS operation.

If the design has correct timing constraints, the timing analysis will tell you, if SignalTap can be implemented without mixing it up. If you get timing violations, it's likely to fail.

thanks a lot!

the frequency of input LVDS signal is 125MHz, the fpga device is EP2C35.

and i have another question , in my project , 4 fpga borad are used and they sample the analog signal synchronously. i wanna they transfer the conversion data in daisy chain. one borad send the data through the lvds tx mega, and the next board recive it through a lvds rx mega. should i enable the tx_clkout of the alt_lvds_tx ?

any other suggestion ?

best regards !

yu.p

125 MHz isn't very fast, but the LVDS unit is using double data rate input registers, as a consequence you can't access the pin state directly by SignalTap.

Serial LVDS transmission is a source synchronous protocol, supplying a clock along with the data is the regular method. Another option is to use a common clock for all FPGAs, but you have to adjust the receiver phase individually and the method won't work at higher data rates due to timing variations.

CDR (clock-from-data recovery) would be a nice option, but it's not provided by Cyclone FPGAs as a regular feature.

Thank you very much FvM .

you really help me a newfish a lot！