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Honored Contributor
Honored Contributorthe signaltab problems
Hi, i am a newfish to the fpga and quartus . during these days, i found a problem about the signaltab ii in quartus 11.0 . My project is used to config a A/D IC, and received the conversion data fro...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- And i want to know if the SignalTab will affect the original logic in the fpga --- Quote End --- Necessarily. You can't tap the high speed LVDS input signals. Recording the deserialized data should be possible, and sufficient to debug LVDS operation. If the design has correct timing constraints, the timing analysis will tell you, if SignalTap can be implemented without mixing it up. If you get timing violations, it's likely to fail.
