Honored Contributor
Honored Contributor125 MHz isn't very fast, but the LVDS unit is using double data rate input registers, as a consequence you can't access the pin state directly by SignalTap.
Serial LVDS transmission is a source synchronous protocol, supplying a clock along with the data is the regular method. Another option is to use a common clock for all FPGAs, but you have to adjust the receiver phase individually and the method won't work at higher data rates due to timing variations. CDR (clock-from-data recovery) would be a nice option, but it's not provided by Cyclone FPGAs as a regular feature.
