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Altera_Forum's avatar
Altera_Forum
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14 years ago

the signaltab problems

Hi, i am a newfish to the fpga and quartus . during these days, i found a problem about the signaltab ii in quartus 11.0 . My project is used to config a A/D IC, and received the conversion data fro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

thanks a lot!

the frequency of input LVDS signal is 125MHz, the fpga device is EP2C35.

and i have another question , in my project , 4 fpga borad are used and they sample the analog signal synchronously. i wanna they transfer the conversion data in daisy chain. one borad send the data through the lvds tx mega, and the next board recive it through a lvds rx mega. should i enable the tx_clkout of the alt_lvds_tx ?

any other suggestion ?

best regards !

yu.p