The problem for using DPA PLL

Hi,

for my project, I need receive 5 channels 500M LVDS sigal and with 50M sync following clock,

I add a PLL for every following clock and generate 50M Phase342, 500M Phase180, 50M Phase288 Duty10 three clocks and connected to serdes.

My FPGA is 5CGXFC7D6F27C7 own 7 PLLs.

Besides these 5 PLL, i also use one for system clock which refclk input is osc. Totally 6 pll, and Place and Route can pass successfully.

In order to improve sampling accuracy, i open the dynamic phase adjust (DPA) function for those 5 PLLs.

When place and route, the error is shown below:

Error (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in regionError (175020): Illegal constraint of fractional PLL to the region (x-coordinate, y- coordinate) to (x-coordinate, y-coordinate): no valid locations in region

is this means if i open DPA function of PLL, the FPGA cannot use 7 PLLs anymore?

How can I solve this problem?

Thanks in advance.

Qi