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Altera_Forum
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8 years ago

The problem for using DPA PLL

Hi, for my project, I need receive 5 channels 500M LVDS sigal and with 50M sync following clock, I add a PLL for every following clock and generate 50M Phase342, 500M Phase180, 50M Phase288 D...
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Altera_Forum
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8 years ago

Insert an ALTCLKCTRL megafunction in the clock path between the dedicated clock input pin and the Altera_PLL. Note, using a global primitive or global signal assignment for the clock signal is not sufficient, the ALTCLKCTRL megafunction must be instantiated in your design.

This is not necessary when the clock input pin has dedicated access to the Altera_PLL.