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Altera_Forum's avatar
Altera_Forum
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15 years ago

The FPGA doesn't work

Hello eveyone:

I'm designing a system of cycloneiii ep3c10e144. The configure chip EPS16 can be written but the FPGA does not work.Could anyone help me checking the scheme pls? The attach is the scheme.

Thanks!

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi everyone:

    The FPGA works well after I connected the bottom pad to GND.Thank all of you.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You're not the first one reading the Cyclone III device manual too casually. The problem has been reported more than once at Altera forum. You'll also find the success story of a clever guy, who managed to drill a hole from the PCB bottom and lately connect the exposed pad.

    I wrongly assumed, that people would always try to connect the device via JTAG in case of any AS configuration problem, which would immediately reveal, that it#s not operating at all.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Yeah, this is a serious mistake. For Cyclone III it must be connected to GND

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks Daixiwen and MADtomato for the answer.I did not connect the pad at the bottom of FPGA to GND. In fact I didn't notice that. I had thougt it is only for heat dissipating. Is it a serious mistake? I will try it as soon as I finish another emergency work.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Were you able to program FPGA with .sof file via JTAG? If not, you should check the behavior of the nStatus pin

    Also you should check the pad at the bottom of FPGA chip. It has to be tied to ground.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I'm guessing you are talking about accessing the flash through the J3a connector?

    If you used JTAG instead and load a SFL image, you'd be able to test the connection between the FPGA and the flash configuration device.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    If you configure your FPGA through JTAG and load a SFL image, can you access the EPCS through JTAG?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi JacoL:

    Thanks for your answer.I've tried as you say,but it didn't work yet. I think if the configure fail,the FPGA's /CEO pin will be high level,But the pin is always low. I doubt that the FPGA is damaged or isn't welded well.I'll check it.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    in normal case it is recommended to put a 25Ohm resistor in the DATA0 Line. I also would remove the capacitors C47, C48. C49 and C50.