The Fitter failed to find a legal placement for IOPLL with DIB of Stratix 10.

I got the next Error from the Fitter while trying to synthesis with DIB

The Fitter Failed to find legal placement for my IOPLL

is there a way to find out which PLL is preferred by the DIB , or vise versa any methodical way to find out which DIB subsystem / channel or bank I choose - since I know what are my free PLL.

(BTW I have many free pll, but somehow they does not good enough for usage by the fitter due to DIB location )

this is the Error I get:

Error (14996): The Fitter failed to find a legal placement for all periphery components
Error (14986): After placing as many components as possible, the following errors remain:
Error (175001): The Fitter cannot place 1 IOPLL.
Info (14596): Information about the failing component(s):
Info (175028): The IOPLL name(s): f1|cnvr_dib_rx_pll_inst|iopll_0|stratix10_altera_iopll_i|s10_iopll.fourteennm_pll
Error (16234): No legal location could be found out of 24 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): There is no routing connectivity between source DIB_DIB_PHY and the IOPLL
Info (175026): Source: DIB_DIB_PHY f1|cnvr_dib_wrapper_ins|dib_rx_2_22|dib_0|dib_ch|arch_inst|phy_inst|xphy_inst
Info (175013): The DIB_DIB_PHY is constrained to the region (442, 290) to (442, 290) due to related logic
Info (175015): The I/O pad DIE1_dib_pad_2_22_0[0] is constrained to the location PIN_DIB0_CH22_X1Y2 due to: User Location Constraints (PIN_DIB0_CH22_X1Y2)
Info (14709): The constrained I/O pad contains this DIB_DIB_PHY
Info (175015): The I/O pad DIE1_dib_pad_2_22_3[22] is constrained to the location PIN_DIB94_CH22_X1Y2 due to: User Location Constraints (PIN_DIB94_CH22_X1Y2)
Info (14709): The constrained I/O pad drives a DIB_DIB_IO_WRP, which drives this DIB_DIB_PHY
Info (175021): The DIB_DIB_PHY was placed in location DIBDIBPHY_X442_Y290_N1
Error (175022): The IOPLL could not be placed in any location to satisfy its connectivity requirements