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Altera_Forum's avatar
Altera_Forum
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11 years ago

The DLL could not be placed in any location to satisfy its connectivity requirements

Hi,

I'm trying to fit a DDR3 memory controller in an Arria V GX device without success. The memory controller is part of a QSys generated system.

This is the message Quartus outputs when failing:

Error (175001): Could not place DLL

Info (175028): The DLL name: cpu_sys_wrapper:i_cpu_sys_wrapper|cpu_sys:i_cpu_sys|cpu_sys_mem_if_ddr3_emif_0:mem_if_ddr3_emif_0|altera_mem_if_dll_arriav:dll0|dll_wys_m

Error (175006): Could not find path between the DLL and destination DQS Group

Info (175027): Destination: DQS Group fed by DQS I/O pad ddr3_dqs_p[2]

Info (175015): The I/O pad is constrained to the location PIN_K2 due to: User Location Constraints (PIN_K2)

Error (175022): The DLL could not be placed in any location to satisfy its connectivity requirements

Info (175021): The DQS Group was placed in location DQS Group containing N3

Info (175029): 4 locations affected

Info (175029): DLL_X4_Y0_N0

Info (175029): DLL_X4_Y90_N0

Info (175029): DLL_X94_Y0_N0

Info (175029): DLL_X94_Y90_N0

Error (175006): Could not find path between the DLL and destination DQS Group

Info (175027): Destination: DQS Group fed by DQS I/O pad ddr3_dqs_p[7]

Info (175015): The I/O pad is constrained to the location PIN_AG6 due to: User Location Constraints (PIN_AG6)

Error (175022): The DLL could not be placed in any location to satisfy its connectivity requirements

Info (175021): The DQS Group was placed in location DQS Group containing AG6

Info (175029): 1 location affected

Info (175029): DLL_X97_Y40_N3

Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter.

I double checked all the DQS & DQ pins are and all seem to be mapped on the correct pins.

Any idea why I'm getting this message?

Thanks,

Didier

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I have the same problem. I want to use Hardware Memory Controller for DDR2 with Cyclone V E FPGA (5CEFA7F27). When I use the HMC located on Top of the FPGA (banks 7A and 8A) the compilation is successful. But when I'm trying to use the second HMC located on the bottom (banks 3B and 4A), i get the same error messages as you do, only with pin locations and signal names from my design. I also tried to compile my design for Cyclone V GX (5CGXFC7D6F26) and received the same results.

    I think it might be an issue with Quartus II fitter due to use of relatively new FPGA's. Altera usually provides some kind of fix or workaround for such problems, but this time i couldn't find any.

    I'm curious to know if anybody else had this issue and how did they deal with it?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I found a solution. As it turns out, the Clock source for the PLL used in memory controller was assigned to a pin, located to far away from the HMC. As soon as i changed the assigned pin to a closer one, the compilation resulted in a successful fit.