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Altera_Forum
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11 years ago

The DLL could not be placed in any location to satisfy its connectivity requirements

Hi, I'm trying to fit a DDR3 memory controller in an Arria V GX device without success. The memory controller is part of a QSys generated system. This is the message Quartus outputs when f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I have the same problem. I want to use Hardware Memory Controller for DDR2 with Cyclone V E FPGA (5CEFA7F27). When I use the HMC located on Top of the FPGA (banks 7A and 8A) the compilation is successful. But when I'm trying to use the second HMC located on the bottom (banks 3B and 4A), i get the same error messages as you do, only with pin locations and signal names from my design. I also tried to compile my design for Cyclone V GX (5CGXFC7D6F26) and received the same results.

I think it might be an issue with Quartus II fitter due to use of relatively new FPGA's. Altera usually provides some kind of fix or workaround for such problems, but this time i couldn't find any.

I'm curious to know if anybody else had this issue and how did they deal with it?