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Altera_Forum's avatar
Altera_Forum
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16 years ago

The difference between the RTL level simulation and the Gate lavel simution

HI! Everyone! I am using Quartus ii web 9.1 . Now There is a problem between the RTL level simulation and Gate lavel simution. I need help! this is the code: LIBRARY IEEE; USE IEEE...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You are right. Maybe I didn't make the question clear before . as long as I spcify initial values to the variables temp and count . the RTL level simulation is OK .

However, AS rbugalho said, " 2. You can add a reset signal to the module and make sure the testbench performs a reset at the beginning of the simulation."

According to his method , I tried and I failed . this is the main problem which is bothering me all the time.

PS: rbugalho is the first respondent to the topic.