The difference between the RTL level simulation and the Gate lavel simution

As I mentioned above, the variables temp and count needs initialization. Without resetting count to a defined value, your design won't work in RTL simulation.

As a side remark. Your above design is using a ripple clock (the output of one process is used as a clock in another process). This is legal VHDL, but not recommended coding style, because it creates timing issues for other signals, that are fed from the first to the second process. You don't have them now, but most likely will in a more complex design.

The problem and possible solutions ("clock enable method") have been discussed frequently in Altera forum and are covered by VHDL text books.