The difference between the RTL level simulation and the Gate lavel simution

It's due the differences in initialization.

In the RTL simulation, the registers are initialized to "X" or "U", since this is what the VHDL and Verilog specifications call for.

In gate level simulation, the registers are initialized to "0", since this is what the FPGA actually does.

There are two ways to handle this.

1. You can specify initial values for the registers.

2. You can add a reset signal to the module and make sure the testbench performs a reset at the beginning of the simulation.