Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The config problem on EP3C10 with EPCS4

Hi, all

I have encountered a trouble in the configuration of EC3C10 by AS mode with EPCS4.

The PCB board was used normally and FPGA can be config successful ago. But i am confused that the FPGA mounted on the same PCB of current lot can not be configured successfully. The QuartusII did not show any error during configuration. I am sure the EPCS4 was uploaded config data successfully, but CONF_DONE of FPGA failed to go high.

I checked MSEL and nStatus, nCONFIG, CONF_DONE,nCE and found that all of them were pullup or pulldown correctly.

Then I test by Oscilloscope find that FPGA output the pulse continuously by DCLK pin. As we know, after finishing the configuration DCLK will go high in normal state.

Were there any other problem can lead to this situation? The FPGA destroyed?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    How do you program and check the EPCS? If you can use a SFL image then you can access the EPCS through the FPGA's pins and check that they are connected properly.

    Did you check the DATA signal between the EPCS and the FPGA with a scope too?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    How do you program and check the EPCS? If you can use a SFL image then you can access the EPCS through the FPGA's pins and check that they are connected properly.

    Did you check the DATA signal between the EPCS and the FPGA with a scope too?

    --- Quote End ---

    Thank Daxiwen! I have upload the pof file to EPCS through programmer and then I unassembly it and mounted in another PCB board, the result is ok. so I am sure the data has been filled to EPCS. But I can not use a SFL image as you suggestion. Maybe I can try it. I have check the DCLK ASDO, DATA0 respectively and find the result as followed.

    DCLK output clock signal in fixed frequency in the process of program, and then DCLK still launch pulse after finishing programming while it must be sticked to high in normal state.

    DATA0 sustain high level after programming

    nSTATUS also generate signal pulse unordered as DCLK while it must be stick to high after programming. This is all I got from Oscilloscope.