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How do you program and check the EPCS? If you can use a SFL image then you can access the EPCS through the FPGA's pins and check that they are connected properly.
Did you check the DATA signal between the EPCS and the FPGA with a scope too?
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Thank Daxiwen! I have upload the pof file to EPCS through programmer and then I unassembly it and mounted in another PCB board, the result is ok. so I am sure the data has been filled to EPCS. But I can not use a SFL image as you suggestion. Maybe I can try it. I have check the DCLK ASDO, DATA0 respectively and find the result as followed.
DCLK output clock signal in fixed frequency in the process of program, and then DCLK still launch pulse after finishing programming while it must be sticked to high in normal state.
DATA0 sustain high level after programming
nSTATUS also generate signal pulse unordered as DCLK while it must be stick to high after programming. This is all I got from Oscilloscope.
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