Altera_Forum
Honored Contributor
13 years agotestbench error on altera quartus 12
Hi,I use testbench to do simulation,but facing error "Error (12061): Can't synthesize current design -- Top partition does not contain any logic
"can anyone help me?here is my verilog code and testbench module FA(cin,x,y,sum,cout); input cin,x,y; output sum,cout; assign sum = (x^y^cin); assign cout = (x&y)|(cin&x)|(cin&y); endmodule `timescale 10ns/1ns module testbench(); reg x,y,cin; wire sum,cout; FA fa1(.cin(cin),.x(x),.y(y),.sum(sum),.cout(cout)); initial begin $monitor($time,"cin=%b,x=%b,y=%b,cout=%b,sum=%b",c in,x,y,cout,sum); end initial begin # 0 cin=0;x=0;y=0; # 50 cin=0;x=0;y=1; # 50 cin=0;x=1;y=0; # 50 cin=0;x=1;y=1; # 50 cin=1;x=0;y=0; # 50 cin=1;x=0;y=1; # 50 cin=1;x=1;y=0; # 50 cin=1;x=1;y=1; end endmodule