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Altera_Forum
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13 years ago

testbench error on altera quartus 12

Hi,I use testbench to do simulation,but facing error "Error (12061): Can't synthesize current design -- Top partition does not contain any logic "can anyone help me?here is my verilog code and tes...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

To simulate use Model Sim. You can invoke Model Sim from Quartus. Go to Menu:

Assignments->Settings->Simulation.

In that Windows Select "Model-Sim Altera" in the box "Tool name".

and in the panel "NativeLink Settings" set "Compile Testbench"

Compile again and then run the ModelSim with Tools->EDA Simulation Tool->RTL Simulation.