Forum Discussion

Honored Contributor

16 years ago

test sram in nios ok,but sram can not be program memory

Hi everyone!

I have a test program for sram like as follows:

alt_u16 *temp=SRAM_16BIT_512K_BASE;

alt_u16 i=0;

alt_u16 data[100];

int main(void)

{

for(i=100;i<200;i++)

{

*(temp+i)=i;

}

temp=SRAM_16BIT_512K_BASE;

for(i=100;i<200;i++)

{

data=*(temp+i);

}

for(i=100;i<200;i++)

{

printf("data[%d]==%d\n",i,data);

}

while(1)

{}

return 1;

}

SRAM_16BIT_512K_BASE =0x80000

It is the address about sram in nios-system,

The result show me that write sram and read sram is ok.

I have also test it in debug module ,with step-in module I can see that memory of sram have been writeen ok.

But when I set sram as program memory ,there are something wrong about it.

Wrong information is :verified 0x80000 and 0x81f70 failed when I run it!

So i wish someone can help me!!:confused:

Altera_Forum
Honored Contributor
16 years ago
I have test that pll output to a i/o pin and check them with oscilloscope ,but without output! If i did not use pll then output was OK!
Altera_Forum
Honored Contributor
16 years ago
what about the 'locked' output of the pll?
Is your source clock connected to a dedicated pll input?
Are you sure the pll is connected to the correct pins?
Are you sure that the input frequency of the pll is the same one than your oscillator?
Do you have any warnings from quartus when you compile your project?
Can you try an empty project with just the pll?
Altera_Forum
Honored Contributor
15 years ago
Try to derive a new clk out from the pll using Altera Mega function Wizard in SOPC B:Take it out throug one I/O pin and check it on a scope