Terasic Apollo S10 SOM_FA

That's a genuinely frustrating situation, and I want to give you a clear technical picture of what's actually happening here, because I think the framing of "Intel CPU vs AMD CPU" is obscuring the real root cause.

The core technical reality: The PCIe endpoint implemented in the Stratix 10 SX FPGA on the Apollo S10 SOM (device 1SX280H) "Apollo S10 SoM" is a hardware interface that operates at the PCIe protocol level — it is completely CPU-architecture-agnostic. Whether your host PC runs an Intel or AMD processor has no bearing whatsoever on whether the FPGA's PCIe hard IP enumerates and links up correctly. PCIe is a standardized bus protocol; the FPGA endpoint does not know or care what brand of CPU is on the other end of the root complex.

Where the real incompatibility is: The problem you're describing — a demo application producing errors when run on an AMD system — is almost certainly in Terasic's host-side software layer: either the demo application itself, or the PCIe device driver it uses to communicate with the endpoint. Some demo software vendors hard-code assumptions based on Intel chipset or CPU-specific timing behaviors, or use CPU-vendor-specific API calls or intrinsics. That is a software bug, not an FPGA design issue, and it is squarely Terasic's responsibility to fix.

On the Quartus version testing request: Asking you to iterate through Quartus Prime Pro versions from 19.1 through 23.3 to test their code is unreasonable, and you are correct to push back on it. The Apollo S10 SOM's published latest supported Quartus version is 20.2.0 "Apollo S10 SoM" — that is the authoritative baseline for this board, and that is where Terasic's own validation should be anchored.

Practical suggestions for you:

• Request in writing from Terasic a clear statement of which host OS, driver version, and software stack their demo has been validated against. "Intel CPU only" is not an acceptable support scope for a PCIe endpoint demo — they need to identify the specific software component that fails.
• If you have access to Quartus Prime Pro 20.2 and the board's design example, you can verify the PCIe link independently by checking whether the endpoint enumerates correctly in your system's device manager/lspci before running any Terasic demo software. Enumeration succeeding (or failing) tells you whether the issue is at the PCIe hardware link level or purely in the demo application.
• The Apollo Carrier board and its associated resources "Apollo S10 SoM" should include a user manual — a User Manual is listed as an included resource for the Apollo S10 SOM. "Apollo S10 SoM" Review that for any host-system requirements Terasic may have documented but not prominently advertised.

You are correct that Terasic, as an Altera partner, has the engineering resources to identify and fix a host-software AMD compatibility issue. That is not end-user test work — it is their product validation responsibility.