New Contributor
Regular ContributorHi,
Where is the exact error/issue happening? The ATX PLL is working fine. So, are you getting issue with the XCVR output? Or is there some data corruption happening at the SATA core?
May I know the reason of change in VCCT and VCCR? The values that they are being changed to, correspond to Arria 10 GT devices, not SoC devices. For SoC devices, the range is from 1.0 V to 1.06V. Please use the PDN tool to find out the dynamic requirements for these power rails,
The VCCT and VCCR voltage levels should be equivalent as per the Pin Connection Guideline. Are we making sure this is happening?
Regards
New ContributorHi,
thanks for the reply.
The errors are happening on the serial link between transceiver and SSD. We get kernel error messages saying that there are disparity or CRC interfaces errors. There is also a signal within the SATA core that is high, when disparity errors occur. We know this is happening by using signal tap. There is no data corruption within the SATA core. We get these errors once the temperature reaches 68°C (we use 1.03V as VCCT and VCCR).
You are right. We already figured out that 0.95V was a wrong setting, so we use 1.03V for VCCT and VCCR (SATA is a "backplane condition", I think you referred to table 4 in the Arria 10 device sheet, I used version 2020.06.26). We do not use different values for VCCT and VCCR (we never did).
We used the PDN tool during the design phase of our custom board.
We also performed the temperature test on the Arria10 SoC Development Kit using the SATA. The interesting fact is that we see the same errors for SATA once we reach 68°C, hence it seems that the occurrence of the errors has nothing to do with the actual hardware. It might be a bitstream/setup issue.
It might be useful that we share more insights about our setup. So, we would like to request for this communication to be handled privately.
Regards
