TCP Ethernet packet in FPGA?

Hmmmm how is the board protocol working then? Do they have TCP/IP stack implemented in there somewhere?

Phew I am mentally exhausted just reading all this. So much to learn. I am not a complete newbie either. I have 5 years of industry experience. I still struggle with all this stuff. Not sure if that's normal.

I started doing these things to once and for all get rid of "I don't know" how to do that feeling. I want to exercise all the components on the board. And just feel satisfied that I did something. Looks like TCP is a bad place to start. I know how to do these:

a) program in verilog

b) Access block rams inside FPGA fabric

c) RTL/FSM design

d) Meeting timing and some knowledge of timing closure.

e) Generate IPs -- PLL, DCM, RAMs, etc....

All my insecurities/fears/whatever it is starts to crop up when I touch peripherals (i.e when I start to do something "real"). I guess I need to attack one component at a time.

I'll set aside TCP for now. I thought I can should with something very simple. How do I get the SSRAM working? I looked at the Altera IP in Quartus I don't see anything called SSRAM controller. Any help truly appreciated. I think you are my Digital Design Teacher hahahaha. I'll do whatever you ask me to implement. I just want to feel secure in my skills :-|